Design of high-speed and low-power finite-word-length PID controllers
A.K.OUDJIDA
N. CHAILLET
A. LIACHA
M. L. BERRANDJIA
M. HAMERLAIN
摘要：ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms: Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer-level (RTL) level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants:set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.
机标关键词：power consumptionPID controllercontrol system
论文发表日期：2014-01-01
在线出版日期：2025-08-15（本平台首次上网日期，不代表文献的发表时间）
页数：16( 68-83 )
英文信息